Synchronizers are logic units which are used to synchronize data between two different clock domains so that data can be transferred from one clock domain to another. Synchronizers are used to resolve meta-stability as quickly as possible. Synchronizers tend to use large devices and extra clock buffering to achieve lower “Tau.” “Tau” is a measure of how quickly meta-stability is resolved i.e., how quickly a sequential unit can decide what the data is when a race condition exists between clock and data. Large sized device usage in a Synchronizer lowers “Tau” at the expense of capacitance on storage nodes of the Synchronizer. These storage nodes are generally critical nodes that hold the state of the sequential unit or latch. Extra capacitance on the storage nodes degrades speed and performance of the Synchronizer.
Even a small change in “Tau” can have a big impact on MTBF (Mean Time Before Failure). Furthermore, reset logic in the Synchronizer memory units (e.g., inside latches, flip-flops) adds devices and hence capacitance to storage nodes. This extra capacitance increases “Tau” and leakage power. On the other hand, state retention and low power objectives demands smaller devices and device stacking to reduce leakage power. It is challenging to incorporate state retention capability into the conventional Synchronizer because smaller devices increase “Tau” (and hence MTBF) while they reduce leakage.